Testing of circuit with plural clock domains

ABSTRACT

An electronic circuit has a plurality of sub-circuits. Clock gate circuits supply gated clock signals to data storage elements of the sub-circuits. The clock gate circuits have gate inputs for receiving gate signals that commands blocking passage of the clock signal. Data can be transferred between data storage elements between two of the subcircuits. A detector circuit flags invalid data in the data storage element of the second one of the sub-circuits. The detector circuit has a flag storage element arranged to set a flag when the clock gate circuit of the second one of the sub-circuits passes the clock signal for the second one of the sub-circuits after the clock gate of the first one of the sub-circuits has blocked the clock signal for the first one of the sub-circuits. The flag indicates the relative phase of the clocks signals of different sub-circuits when the clocks are stopped. The flag is used to invalidate data in the data storage element of the second one of the sub-circuits.

The field of the invention is an electronic circuit that comprises aplurality of clock domains and a method of testing such an electroniccircuit.

For a number of reasons integrated circuits are increasingly split intomultiple clock domains that have their own clocks signals (this splitusually occurs only in a functional sense, not physically). The use ofdifferent clock domains lowers the requirements on skew of the clocksignals used for different sub-domains and it can be used to reducepower consumption by the circuit for example. In a circuit with multipleclock domains the clock signals of different clock domains are mutuallydifferent for example in terms of phase, frequency or duty cycle etc. Ineach domain the supply of the clock signal to sub-circuits in that clockdomain can be switched off independently from the other clock domains.

Unfortunately the use of different clock domains makes testing anddebugging of the electronic circuit more difficult. U.S. Pat. No.6,131,173 describes a solution to mitigate these difficulties. At theinterface between two clock domains an interface circuit is insertedthat can isolate the different clock domains from one another in a testmode. This interface makes it possible to supply or extract test data toor from the isolated clock domains.

This technique, however, does not make it possible to test or debug thesub-circuits from different clock domains when they cooperate with oneanother. To debug such cooperative operation it is necessary to allowthe sub-circuits to cooperate while each is clocked with its own clocksignal. Upon a stop request from the tester, debugger or on-chip debughardware, the clocks are stopped in order to inspect the data producedduring the cooperation of the circuits. However, it has been found thatsuch a method of debugging does not always produce reliable results. Forexample, comparison of the data produced during cooperation does notconsistently match simulation data, even when the circuit is operatingproperly.

Amongst others, it is an object to facilitate debugging and testing ofelectronic circuits that contain multiple clock domains in whichsub-circuits from different clock-domains cooperate with one another.

The electronic circuit according to the invention is set forth in claim1. It has been realized that the unreliability of the results ofdebugging is a consequence of the fact that it is impossible to stop theclocks in different clock domains simultaneously. For example, it isusually necessary to complete the current clock cycle before the clockcan be stopped. Thus, due to phase and frequency differences between thedifferent clock signals, the clock of a first clock domain may bestopped before the clock of a second clock domain.

This may have the effect that a data storage element in the second clockdomain captures invalid data, more in particular data that should havebeen updated before it was captured, but was not updated because theclock signal of the first clock domain was stopped before the update.This happens when an active part of a clock signal that controls updatedata in the data storage element in the first clock domain is suppressedin the time interval between the signal to stop the clocks and the timewhen data is captured by the data storage element in the second clockdomain (the active part may be an clock signal edge in case of a edgetriggered data storage elements, or a pulse in case of pulse triggereddata storage elements etc.). In the prior art the debugger or testercannot see whether this has happened or not. Therefore this may lead tomisleading conclusions about the operation of the circuit.

According to the invention a detector is provided accompanying theinterface between a first and second one of the sub-circuits fromdifferent clock-domains. The detector is arranged to detect theconditions under which data is captured when the clocks of thesub-circuits are stopped. In a sense it determines the phase relationbetween the clock signals to the extent that this phase relation isrelevant for data transfer between clock domains at the time when theclock signals are stopped. This enables the tester or debugger toevaluate the captured data properly, for example by discarding data thathas been captured too late.

In an embodiment of the invention the detector is implemented with apair of flag storage elements. The first flag storage element sets apre-flag in response to the clock signal of a first sub-circuit whenthat clock signal is no longer passed to the first sub-circuit and thesecond flag storage element copies the pre-flag in response to the clocksignal of the second sub-circuit when that clock signal is passed to thesecond sub-circuit. Thus, the flag represents whether the clock signalof the second circuit has caused data to be captured after the clock ofthe first sub-circuit has been blocked.

In another embodiment a pipeline data storage element is added to thedata storage element of the second sub-circuit. The pipeline datastorage element stores overwritten data from the data storage element.Thus, both data for a clock cycle and a preceding clock cycle isretained and the one or the other may be used dependent on whether theflag is set. In this way consistent data can be assured.

Preferably both the flag and the data can be read out via a conventionalscan chain when the clocks have been stopped, or, as an alternative, theflag can control which data is read out via the scan chain.

These and other objects and advantages of the electronic circuitaccording to the invention and of the method of testing this circuitwill be described in more detail using the following figures.

FIG. 1 shows an electronic circuit with multiple clock domains.

FIG. 2 shows signals that occur during operation.

FIG. 3 shows a detection circuit.

FIG. 4 shows an electronic circuit with multiple clock domains.

FIG. 5 shows a detail of an electronic circuit.

FIG. 1 shows an electronic circuit with multiple clock domains. Thecircuit contains clock circuitry 10, two clock domains 12 a,b, with afirst storage element 120 and a second storage element 122 respectively,clock gating circuits 14 a,b and a detector 16. The first storageelement 120 has a data output coupled to a data input of the secondstorage element 122. Although a direct connection is shown, it will beappreciated that this connection may run via combinatorial logiccircuits (not shown). Clock outputs of the clock circuitry 10 arecoupled to the clock inputs of the first and second data storage element120, 122 via the respective clock gating circuits 14 a,b. Furtherstorage elements (not shown) may be present in the clock domains 12 a,b,possibly coupled to each other inside the domains via combinatoriallogic circuits (not shown). These further data storage elements are alsoclocked by the clock signals from the respective clock gating circuit 14a,b. Similarly, although a single output and input are shown for datastorage elements 120, 122, it will be clear that this output and inputmay provide for a single bit or multiple bits. All circuits arepreferably included on the same integrated circuit, but of coursecircuits distributed over different integrated circuits may be usedinstead.

By way of example both clock gating circuits 14 a,b are shown to have asimilar structure, containing a first flip-flop 140, a second flip-flop142 and an AND gate 144. A clock output from clock circuitry 10 iscoupled to clock inputs of first and second flip-flop 140, 142 and to afirst input of AND gate 144. A data input 148 of the first flop-flop 140forms a clock gate command input of the clock gating circuit 14 a. Adata output of the first flip-flop 140 is coupled to a data input of thesecond flip-flop 142. A data output of the second flip-flop 142 iscoupled to a second input of the AND gate 144. The output of the ANDgate 144 is coupled to a clock input of the clock domain 12 a, where itis coupled to the clock input of the first storage element 120.Similarly, the clock gating circuit 14 b of the second sub-circuit has aclock gate command input, a clock input coupled to clock circuitry 10and a clock output coupled to the clock input of second clock domain 12b, where it is coupled to the second storage element. The first andsecond input of the AND gate 144 and the clock output of clock gatingcircuit 14 b of the second sub-circuit are coupled to the detector 16.

It will be appreciated that the precise structure of the clock gatingcircuits is shown for illustration purposes only. Without deviating fromthe invention any other type of clock gating circuit that allows gatingof clock signals may be used.

In operation, clock gating circuits 14 a,b normally pass clock signalsfrom the clock circuitry 10 to clock domains 12 a,b. When a stop signalis asserted at the clock gate command inputs of the clock gatingcircuits 14 a,b these clock gating circuits 14 a,b block passage of theclock signals to their respective clock domains 12 a,b after a completeclock cycle has occurred. Detector 16 detects whether data is loadedinto second data storage element 122 when that data has been affected bythe fact that data was not loaded into first data storage element 120after the stop signal has been asserted.

FIG. 2 shows signals occurring during operation. A first and secondtrace show clock signals CLK1, CLK2 output by clock circuitry 10 toclock gating circuits 14 a,b. A third trace shows a stop signal STOPwhich is applied to the clock gate command inputs of the clock gatingcircuits 14 a,b. A fourth and fifth trace show gated clock signalsGCLK1, GCLK2 that the clock gating circuits 14 a,b pass to clock domains12 a,b. A sixth trace shows the signal FLAG output by detector 16.

The signal STOP causes the clock gating circuits 14 a,b to pass only onepositive clock pulse 20, 22 after the STOP signal has been asserted.Subsequently the clock signal is blocked. When the STOP signal is notasserted AND gate 144 passes all clock pulses. On the rising edge ofthis clock pulse 20, 22 the first flip-flop 140 copies the STOP signalfrom the clock gating command input 148. On the falling edge of thisclock pulse 20, 22 the second flip-flop 142 copies the STOP signal whichthen disables AND gate 144 from passing further clock pulses. Detector16 monitors whether AND gate 144 receives any clock pulses after ANDgate 144 has been disabled from passing further clock pulses. If thishappens and subsequently second clock gating circuit 14 b outputs aclock pulse detector 16 sets its output signal FLAG to indicate thatsecond data storage element 122 may have captured invalid data.

FIG. 3 shows an example of an implementation of detector 16. Thisimplementation contains a first flip-flop 30 and a second flip-flop 32.The clock suppressing signal from first clock-gating circuit 14 a (fromthe output of the second flip-flop 142 in that first clock-gatingcircuit 14 a) is applied to a data input 36 of first flip-flop 30. Thisfirst flip-flop 30 receives the ungated clock signal CLK1 of first clockgating circuit 14 a at a clock input 34. The data output of firstflip-flop 30 is coupled to a data input of second flip-flop 32. Secondflip-flop 32 has a clock input 38 coupled to the gated clock output ofsecond clock gating circuit 14 b (outputting GCLK2). A data output 39 ofsecond flip-flop 32 supplies output signal FLAG of detector 16.

In operation, first flip-flop 30 of detector 16 is set when first clockgating circuit 14 a suppresses a clock pulse. This set data from firstflip-flop 30 is copied to second flip-flop 32 when that second flip-flop32 is clocked after the clock pulse. First flip-flop 30 and secondflip-flop 32 mimic first and second data storage element 120, 122 todetect whether invalid data may be captured by the second data storageelement. Copying of predetermined flag data by second flip-flop 32 isindicative of copying of invalid data by second data storage element122. The predetermined flag data is set-up because a difference betweenflip-flops 30, 32 and data storage elements 120, 122 is that firstflip-flop 30 receives the ungated clock, i.e. the clock that should bepresent to produce valid data for second data storage element 122, andthat predetermined flag data (the STOP signal) is loaded into firstflip-flop 30 when the clock signal is suppressed.

It will be noted that there may be timing differences between clocksignals applied to the data storage elements 120, 122 and clock signalsapplied to detector 16, for example due to differences in the delayexperienced by the clock signals before they reach the respectivecircuits. This is no problem when detector 16 is made to detect aworst-case situation. Preferably, therefore, it is ensured that thedelay experienced by the first domain clock signals that are used indetector 16 is shorter than (or at least as short as) the delay withwhich these signals are applied to the first domain 12 a, while thedelay experienced by the second domain clock signals that are used indetector 16 is longer than (or at least as long as) the delay with whichthese signals are applied to the second domain 12 b.

It will be appreciated that the selection of the clock edges at whichfirst and second flip-flop 30, 32 in detector 16 load informationcorresponds to the clock edges at which data first and second storageelements 120, 122 load data. So if second storage element loads data onnegative clock edges, for example, second flip-flop 32 preferably loadsthe flag on negative clock edges as well. The same goes for the firstflip-flop 30 of detector 16 with respect to first data storage element120 and for dual edge triggering, pulse controlled data loading etc.

It will be appreciated that the invention is not limited to theimplementation of the detector 16 shown in FIG. 3, or to using theparticular signals used by that detector. Any detector may be used thatdetects whether a clock pulse is output to second clock domain 12 bafter a pulse from first clock gating circuit 14 a has been suppressed.Similarly it will be appreciated that any way of stopping the clocks maybe used, for example passing a greater or lesser part of the clocksignals after assertion of the stop signal, as long as detector 16detects whether an active clock edge occurs from second clock gatingcircuit 14 b after an active clock edge from first clock gating circuit14 a has been suppressed.

In practice, various circuits may be added in order to protect transferof data from the first clock domain 12 a to the second clock domain 12 bin order to prevent a change of data in the data storage element 122close to the point in time when the data in the other data storageelement 120 is changed. This may be implemented by any known means, suchas handshake signals, semaphores, clock arbiters at the clock input ofthe storage elements etc. However, such means have been omitted from thefigures for the sake of clarity, since they do not affect the timingrelation between the clock signals, but only the data transferred. Thedetection principle for determining the timing relation between theclock signals remains the same.

FIG. 4 shows an electronic circuit with three clock domains. In additionto the clock domains 12 a,b a third clock domain 12 c with a third clockgating circuit 14 c is shown. The first data storage element 120 of thefirst clock domain 12 a is coupled to the third clock domain 12 c. Thus,invalid data transfer may occur from the first clock domain 12 a, toboth the second and third clock domain 12 b,c. When the second and thirdclock domain 12 b,c have independent clocks this may occur independentlyfor the second and third clock domain 12 b,c. In principle, separatedetectors may be provided to detect this. However, when detectorssimilar to the one shown in FIG. 3 is used, the first flip-flop 30 ofthe detector may be shared by the second and third domain 12 b,c, onlythe second flip-flop 32, 40 being provided separately for the differentdomains 12 b,c. Of course, more second flip-flops 32, 40 may be providedwhen first domain 12 a interfaces to more than two domains 12 b,c.

As shown, the circuit allows detection of copying of invalid data in thesecond clock domain 12 b, but no correction. Thus, if it is necessary toinspect the data captured by the second data storage element 122 thecircuit may have to be restarted a number of times until detector 16indicates that no invalid data has been captured. If desired, this maybe obviated by adding a pipeline of one or more data storage elements tosecond data storage element 122, for storing successive data values thathave been stored in second data storage element 122 previous to currentdata. In this case, the relevant data may be selected from the pipelineon the basis of the output signal of the detector.

Any means may be used to read data from the data storage elements 120,122 and to read detection results from detector 16. For example, aconventional scan chain may be used for this purpose.

FIG. 5 shows an example of part of an electronic circuit that providesfor correction. The second clock domain 12 b and its corresponding clockgating circuit 14 b are shown, together with detector 16. The secondclock domain 12 b is shown to contain a pipeline storage element 50, amultiplexer 52 and part of a scan chain 54. An output of the second datastorage element 122 is coupled to the pipeline storage element 50. Theoutput of the second data storage element 122 and the pipeline storageelement 50 are coupled to inputs of the multiplexer 52, which has anoutput coupled to the scan chain 54. The flag output of detector 16 iscoupled to a control input of multiplexer 52.

In operation, each time data storage element 122 loads new data, theprevious data in data storage element 122 is copied into pipelinestorage element 50. Thus, when clock gating circuit 14 b stops supplyingclock signals to second clock domain 12 b, data storage element 122contains data captured in the last clock cycle and pipeline storageelement contains data captured by data storage element 122 in the beforelast clock cycle. Multiplexer 52 passes the latter to scan chain 54 whendetector 16 indicates that a clock cycle in the first clock domain 12 ahas occurred before data storage element 122 has captured data in thelast clock cycle before its clock was stopped. Otherwise, multiplexer 52passes data from the data storage element 122 to the scan chain 54.Thus, the appropriate test data is passed to scan chain 54.

It will be appreciated that other means than a scan chain can be used toread out the data, or that data from both the data storage element 122and pipeline storage element 50 may be read out, together with theoutput of detector 16 to test or debug the circuit. The circuit of FIG.5, however, has the advantage that a minimum of information needs to beread out.

1. An electronic circuit comprising: clock circuitry; a firstsub-circuit comprising a first clocked data storage element and a firstclock gate circuit that is coupled between an output of the clockcircuitry and a clock input of the first data storage element; a secondsub-circuit comprising a second data storage element, within a differentclock domain as the first data storage element, and a second clock gatecircuit that is coupled between an output of the clock circuitry and aclock input of the second data storage element; a data path between thefirst clocked storage element and the second clocked storage element; adetector circuit, coupled between the first sub-circuit and the secondsub-circuit, that flags an invalid data write operation in the seconddata storage element in relation to the first clocked gate circuitreceiving a gate signal that commands blocking passage of a first clocksignal from the clock circuitry.
 2. The electronic circuit of claim 1wherein the detector circuit comprises: a pre-flag storage element thatsets a pre-flag in response to the first clock signal from the clockcircuitry being blocked; and a first flag storage element that copiesthe pre-flag in response to the second clock gate circuit passing asecond clock signal for the second sub-circuit.
 3. The electroniccircuit of claim 2 further comprising: a third sub-circuit comprising, athird clocked data storage element and a third clock gate circuit, thatis coupled to receive data from the first clocked data storage element;and wherein the detector circuit further comprises a second flag storageelement that copies the pre-flag in response to the third clock gatecircuit passing a third clock signal for the third sub-circuit.
 4. Theelectronic circuit of claim 1 further comprising a pipeline storageelement coupled to the second clocked data storage element for copyingdata from the second clocked data storage element to preserveerroneously overwritten in the second clocked data storage element. 5.The electronic circuit of claim 4 comprising an output circuit forreading data from the second clocked data storage element and thepipeline storage element in response to a flag not being appropriatelyset.
 6. The electronic circuit of claim 1 further comprising a scanchain, coupled to a flag storage element and the second clocked datastorage element, that allows a flag and data from the second datastorage element to be read.
 7. A method of testing an electronic circuitcontaining a plurality of clocked data storage elements, the methodcomprising: operating a first clocked data storage element, within theplurality of clocked data storage elements, in a first clock domain;operating a second clocked data storage element, within the plurality ofclocked data storage elements, in a second clock domain that isdifferent than the first clock domain; commanding a plurality of clockgate circuits, associated with the plurality of clocked data storageelements, to block passage of at least one clock signal; detecting awrite error at the second clocked data storage element caused by thecommand to block passage of at least one clock signal; and correctingthe write error at the second clocked data storage element.
 8. Themethod of claim 7 wherein the write error is detected by removing a flagin response to a complete write operation by the second clocked datastorage element.